Democratizing IC Design and Customized Computing
Jason Cong
UCLA Computer Science Department
Director, Center for Domain-Specific Computing (CDSC)
http://vast.cs.ucla.edu/people/faculty/jason-cong
The electronic design automation (EDA) traditionally serves the hardware design community. As we enter the era of customized computing with increasing amount of computation moves from general-purpose CPUs to domain-specific accelerators (DSAs) due to their performance and energy efficiency, there is a pressing need and opportunity for the EDA community to empower millions of software programmers to create their own DSAs to accelerate the compute-intensive portion of their applications. High-level synthesis (HLS) made an important progress in this direction, but far from sufficient. In this talk, I shall discuss the recent progresses in this area, including microarchitecture guided optimization, such as automated systolic array generation, automated source-to-source transformation based on graph-based neural networks and meta learning, and support of domain-specific languages widely used in the software community. I hope to see the ICCAD community in joining the effort of broadening the participation of IC designs and customized computing.
Speaker Bio:
Jason Cong is the Volgenau Chair for Engineering Excellence Professor (and former Department Chair) at the UCLA Computer Science Department, with joint appointment from the Electrical Engineering Department, the director of Center for Domain-Specific Computing (CDSC), and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory. Dr. Cong’s research interests include electronic design automation, novel architectures and compilation for customizable computing, and quantum computing. He has close to 500 publications in these areas, including 16 best paper awards, three 10-Year Most Influential Paper Awards, and three papers inducted to the FPGA and Reconfigurable Computing Hall of Fame. He and his former students co-founded AutoESL and Falcon Computing Solutions. Both were acquired by Xilinx and led to the most widely used high-level synthesis tool for FPGAs. He was elected to an IEEE Fellow in 2000, ACM Fellow in 2008, and the National Academy of Engineering in 2017. He is the recipient of the 2022 IEEE Robert Noyce Medal for fundamental contributions to electronic design automation and FPGA design methods.
Automated Cryptographically-Secure Private Computing: From Logic and Mixed-Protocol Optimization to Centralized and Federated ML Customization
Farinaz Koushanfar
Henry Booker Scholar Professor of ECE at the University of California San Diego (UCSD)
Over the last four decades, much research effort has been dedicated to designing cryptographically-secure methods for computing on encrypted data. However, despite the great progress in research, adoption of the sophisticated crypto methodologies has been rather slow and limited in practical settings. Presently used heuristic and trusted third party solutions fall short in guaranteeing the privacy requirements for the contemporary massive datasets, complex AI algorithms, and the emerging collaborative/distributed computing scenarios such as blockchains.
In this talk, we outline the challenges in the state-of-the-art protocols for computing on encrypted data with an emphasis on the emerging centralized, federated, and distributed learning scenarios. We discuss how in recent years, giant strides have been made in this field by leveraging optimization and design automation methods including logic synthesis, protocol selection, and automated co-design/co-optimization of cryptographic protocols, learning algorithm, software, and hardware. Proof of concept would be demonstrated in the design of COINN, the present state-of-the-art framework for cryptographically-secure deep learning on encrypted data. We conclude by discussing the practical challenges in the emerging private robust learning and distributed/ federated computing scenarios as well as the opportunities ahead.
Speaker Bio:
Farinaz Koushanfar is the Henry Booker Scholar Professor of ECE at the University of California San Diego (UCSD), where she is also the founding co-director of the UCSD Center for Machine-Intelligence, Computing & Security (MICS). Her research addresses several aspects of secure and efficient computing, with a focus on hardware and system security, robust machine learning under resource constraints, intellectual property (IP) protection, as well as practical privacy-preserving computing. Dr. Koushanfar is a fellow of the Kavli Frontiers of the National Academy of Sciences and a fellow of IEEE. She has received a number of awards and honors including the Presidential Early Career Award for Scientists and Engineers (PECASE) from President Obama, the ACM SIGDA Outstanding New Faculty Award, Cisco IoT Security Grand Challenge Award, MIT Technology Review TR-35, Qualcomm Innovation Awards, Intel Collaborative Awards, Young Faculty/CAREER Awards from NSF, DARPA, ONR and ARO, as well as several best paper awards.
Atoms to Silicon to Systems Hyper-convergence: The Way Forward in the Angstrom Era
Shankar Krishnamoorthy
General Manager, EDA Group, Synopsys
AI, fueled by semiconductor compute power, is driving the growing intelligence in the ‘smart everything’ world we live in. Silicon is at the heart of the new wave of products enabling this intelligence. At the same time, chips’ scaling, performance, energy efficiency and cost are being challenged like never before.
In this keynote, Shankar Krishnamoorthy, general manager of the EDA Group at Synopsys shares his views on why it is imperative for the semiconductor industry to take a holistic atoms to silicon to systems approach to address these challenges and what solutions are needed to realize the next wave of semiconductor innovations.
Speaker Bio:
Shankar Krishnamoorthy, GM, EDA Group, leading the team behind the design and verification software platforms from Synopsys. His group innovates across a broad spectrum of EDA technologies including simulation, static analysis, debug, synthesis, signoff analysis, place-and-route, test automation, and formal verification solutions. Prior to this role, he was General Manager of the Digital Design Group, with responsibility for the Synopsys digital design platform. In earlier roles, he served as Senior Vice President of the Digital Implementation Group, delivering several game-changing innovations including Fusion Compiler™, RTL Architect, 3DIC Compiler, and TestMAX solutions. Before rejoining Synopsys in 2017, Shankar was at Mentor Graphics, where he served as General Manager of the IC Design Solutions Division. He joined Mentor in 2007 with the acquisition of Sierra Design Automation, where he was Founder and CTO. Prior to Sierra Design, Shankar led Synopsys’ physical synthesis and logic synthesis R&D organizations. Shankar received his M.S. in Computer Science from the University of Texas, Austin, and his bachelor’s degree in Computer Science from the Indian Institute of Technology, Bombay.
